(1) Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device such as a metal-insulator semiconductor (MIS) random access memory (RAM) device in which when an input address signal is switched erroneous write in is prevented.
(2) Description of the Prior Art
As illustrated in FIG. 1, a conventional MIS static-type RAM device comprises memory cells MC which are respectively connected between word lines W1, W2, - - - and bit line pairs B0 and B1, - - - . Although the RAM device comprises a plurality of bit line pairs, only a single bit line pair B0 and B1 is illustrated in FIG. 1. Each of the memory cells MC, for example, memory cell MC0, comprises load resistors R1 and R2, a flip-flop circuit comprising MIS transistors Q1 and Q2, and transfer gates each comprising MIS transistor Q3 or Q4. One end of each of the bit lines B0 and B1 of the bit line pair is connected to the power source V.sub.CC through transistors Q5 and Q6, respectively. The other end of each of bit lines B0 and B1 is connected to data buses DB and DB0 through column-selecting transistors Q7 and Q8.
In the RAM device of FIG. 1, when the potential of a word line, for example, W1, is changed from low to high, transistors Q3 and Q4 are turned on and memory cell MC0 is connected to the pair of bit lines B0 and B1. In this state, if column-selecting signal Y1 is changed from low to high, transistors Q7 and Q8 are turned on and bit lines B0 and B1 are connected to data buses DB and DB respectively. Thereby, memory cell MC0 disposed at the intersection between word line W1 and the pair of bit lines B0 and B1 is selected. When the memory cell MC0 is selected, if the potentials of bit lines B0 and B1 are rendered to be high and low, respectively, through data buses DB and DB transistor Q2 of the memory cell MC0 is turned on and transistor Q1 thereof is turned off, thereby effecting the writing in of data. In order to read out data thus written in, the potentials of word line W1 and column-selecting signal Y1 are pulled up to high. In this case, when the potential of the word line W1 changes from low to high, transistors Q3 and Q4 are both turned on, and the relatively high potential of a point a and the relatively low potential of a point b of memory cell MC0 are transferred to bit lines B0 and B1, respectively. The potentials of bit lines B0 and B1 thus transferred from the memory cell MC0 are transferred to a readout circuit (not shown) through transistors Q7 and Q8 and data buses DB and DB
When information is written into a memory cell of a semiconductor memory device, write-enable signal WE is supplied to the memory chip of the semiconductor memory device. In the semiconductor memory device, write-enable signal WE is supplied to a buffer circuit, i.e., an inverter circuit, and inverted signal WE0 of write-enable signal WE output therefrom changes the memory device from a readout mode to a write in mode. A memory cell in which data is written in or a memory cell in which data is read out is designated by an address signal. The address signal has a plurality of bits, and some of the upper bits and all of lower bits are, respectively, used as a word address signal for selecting a word line and as a bit address signal for selecting a pair of bit lines.
As illustrated in FIG. 2, if, at time t2, input address signal A has changed so that word line Wi which was selected changes to a non-selected condition and word line Wj is selected instead of word line Wi, the potential of word line Wi changes from high to low and the potential of word line Wj changes from low to high. In this case, since the fall time of the potential of the word line Wi and the rise time of the potential of the word line Wj can not be negligibly small, there occurs a condition in which the potentials of word lines Wi and Wj both become high. In this condition, if the potentials corresponding to data to be written in next are applied to a bit line pair, the erroneous write in of data is possible, that is, there is a possibility that the data to be written in next will be written into memory cell MC0 in which data has just been written in.
In order to prevent such a phenomenon, a conventional memory device inhibits the writing of data in a memory cell for a short time during the switching period of input address signal A by rendering write-enable signal WE low and inverted write-enable signal WE0 high. As illustrated in FIG. 3, an input/output circuit of a conventional memory device comprises an output stage which comprise transistors Q11 through Q18 and inverter N1 and which receives readout data DO from, for example, a sense amplifier (not shown), and an input stage having input data buffer IDB which supplies write in data to a pair of data buses. The output stage of the input/output circuit of FIG. 3 comprises a series circuit of transistors Q11 and Q12 whose output terminal P1 is connected to I/O port IOP which is also connected to an input terminal of input data buffer IDB. The series circuit of transistors Q11 and Q12 exhibits three states, i.e., a state of high potential level, a state of low potential level, and a state of high impedance.
When writing of data into the memory device is effected, transistors Q11 and Q12 are both turned off and the output stage is in a high impedance state so that write in data Di is transferred from I/O port IOP to input data buffer IDB without being affected by the output stage. In order to obtain a high impedance state, external write-enable signal WE is applied to the gates of transistors Q15 and Q18. Transistors Q15 and Q18 are connected in parallel with transistors Q14 and Q17, respectively, and connected in series with transistors Q13 and Q16, respectively. Transistors Q13 and Q14 and transistors Q16 and Q17 constitute inverters whose outputs are both rendered low by external write-enable signal WE. That is, when external write-enable signal WE is high, transistors Q15 and Q18 are both turned on and outputs P2 and P3 of the upper stage inverter and the lower stage inverter both become low. Therefore, transistors Q11 and Q12 are both turned off and the impedance of the output stage becomes high.
When readout of data from the memory device is effected, external write-enable signal WE is rendered to be low so that transistors Q15 and Q18 are both turned off. Transistor Q14 is turned on and off and transistor Q17 is turned off and on in accordance with the high and low, i.e., "1" and "0", of readout data DO. Therefore, output signal P2 becomes low and high, and output signal P3 becomes high and low in accordance with the high and low of readout data DO so that output signal P1 of the final stage comprising transistors Q11 and Q12 becomes low and high. Output signal P1 is transferred to I/O port IOP without being affected by input data buffer IDB because input data buffer IDB has a high input impedance.
As mentioned before, in the input/output circuit of FIG. 3, write-enable signal WE must be rendered low every time the input address signal changes its state, even when write in is continuously effected. When write-enable signal WE is low, transistors Q11 and Q12 of the output stage change from a condition in which transistors Q11 and Q12 are both turned off to a condition in which one of transistors Q11 and Q12 is turned on and the other is turned off. When write-enable signal WE again becomes high, transistors Q11 and Q12 both are again turned off. Therefore, transistors Q11 and Q12 of the output stage repeatedly change their condition from one in which they are both turned off to one in which one of them is turned on and the other is turned off and vice versa. Since the size of each of transistors Q11 and Q12 of the output stage is large and the stray capacitances between the gate and the drain and between the gate and the source, etc., are large, the rise time and the fall time of output signal P1 becomes long and the effective time for the write in operation becomes short. Therefore, it is necessary to increase the write in time so that the write in speed is slow.
In order to avoid a condition in which the potential of the word line Wi, which is selected first, and the potential of the word line Wj, which is selected after word line Wi, are both high, it is possible to put time interval T between the switching times of the signals on word lines Wi and Wj, as shown by Wi' and Wj' of FIG. 2, when a selected word line is switched from Wi to Wj. In this method, external write-enable signal WE is maintained at a high level during a continuous write in period, and it is not necessary to render the write-enable signal low every time the input address signal changes its state.
However, putting time interval T between the switching times of the signals on the word lines Wi and Wj requires word line drivers having complex structures, and, moreover, the readout time of a memory device employing such a system becomes long.